As part of my academic research project (part of Compilers for Embedded Systems course), I had developed a Morphosys[1]-like cycle-accurate Coarse Grained reconfigurable architecture simulator which was integrated with simplescalar[2]. This simulator executes simple RISC instructions along with special morphosys instructions which are executed in a SIMD like parallel fashion on 8x8 reconfigurable cells. The simulator is cycle-accurate and the number of cycles taken is displayed as a part of output. This simulator helps in the understanding the underlying CGRA architecture and provides as a basis for further enhancement or portability to suit other CGRAs (For e.g., to convert this simulator to RSPA architecture, we need to implement Pipelined RC execution, shared resources and local configuration cache. So we need to modify existing RC execution steps to include Pipelining, local context memory should be implemented instead of global one present in current code)
As it is integrated with simplescalar simulator, enhancement and/or bug fixes should be fairly easier. Also, since simplescalar tool comes with gcc compiler, application mapping included in gcc for simplescalar has greater useability.
For more information, code, docs and installation instructions, please refer to
http://www.public.asu.edu/~scmarath/ (section Projects(code and docs))
References:
1. Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, “MorphoSys: An Integrated Reconfigurable System for Data-Parallel Computation-Intensive Applications”
