Some background (can be skipped):
I had got a Spartan 3E Starter kit a couple of years back to learn some hardware design and VHDL/Verilog programming. Since then, I made a conscious decision to stay in software, and part of that thought was to learn Linux internals. So here I am, eager to dig deep in Linux bringup and driver development, to gain more knowledge on top of what I have done as my career work.
So, without much ado, lets start with the project details.
Project Goal:
To bringup U-boot on a 32-bit Microblaze based Spartan 3E FPGA.
***Petalogix has already done U-boot porting for Spartan 3E and their commercial releases are sold for a fee. This effort provides an alternative for people who dont want to approach Petalogix and shell out any fee :)
Is Xilinx Spartan 3E FPGA board, Rev. D from Digilent. The FPGA has a 32-bit MIPS based Softcore IP (Microblaze) and peripherals include 64MB DDRAM, 16MB Flash, 2MB SPI Flash, 10/100M Ethernet PHY, VGA connector, RS-232 DCE, DTE etc.
- Hardware Details
Is Xilinx Spartan 3E FPGA board, Rev. D from Digilent. The FPGA has a 32-bit MIPS based Softcore IP (Microblaze) and peripherals include 64MB DDRAM, 16MB Flash, 2MB SPI Flash, 10/100M Ethernet PHY, VGA connector, RS-232 DCE, DTE etc.
The complete user guide is here: http://www.digilentinc.com/Data/Products/S3EBOARD/S3EStarter_ug230.pdf
H/w Tools used:
Xilinx Platform Studio EDK, ISE 10.1, XMD (for on board USB based debugger)
Xilinx Platform Studio EDK, ISE 10.1, XMD (for on board USB based debugger)
Hardware Design:
Assuming that folks are aware of FPGA design in general and have used Xilinx EDK, let me point out the considerations specific to our design
-Using BSB, created a new design for Spartan 3E rev.D with Microblaze processor, with 50MHz core clock (and PLB clock), selected following peripherals:
-Using BSB, created a new design for Spartan 3E rev.D with Microblaze processor, with 50MHz core clock (and PLB clock), selected following peripherals:
RS-232 UART Lite instance (with interrupt), XPS interrupt controller, XPS timers(2 instances), GPIO- LED module, Flash (16MB), DDRAM (64MB)
- Select Ethernet EmacLite (note, if using TriEthernet, then the processor clock has to be increased)
- Add I-, D-, caches (default 2K each). Use BRAM (with default local Memory Bus (LMB) interface) for caches.
- Add software application project to have memory and peripherals test to the project.
*imp* Make sure these tests pass
- Select Ethernet EmacLite (note, if using TriEthernet, then the processor clock has to be increased)
- Add I-, D-, caches (default 2K each). Use BRAM (with default local Memory Bus (LMB) interface) for caches.
- Add software application project to have memory and peripherals test to the project.
*imp* Make sure these tests pass
Modifying hardware config:
- Enable MMU. MMU is disabled by default. Enable them by modifying Microblaze IP (enable MMU to to Full, Virtual Mode operation)
- Change Cache to disable D-Cache and enable only I-Cache(of size 4K). *imp*
Found this out after running through weird issues in U-boot. For D-cache to be enabled; we need to have atleast 8K cache itseems (found in some Xilinx document); but Spartan 3E being a starter kit has just 4K cache. So we cannot have D-cache enabled.
Found this out after running through weird issues in U-boot. For D-cache to be enabled; we need to have atleast 8K cache itseems (found in some Xilinx document); but Spartan 3E being a starter kit has just 4K cache. So we cannot have D-cache enabled.
- *imp* Modify Flash address to be placed higher than RAM address range. (U-boot needs it that way)
My final address map looked like this:
Address Map for Processor microblaze_0
(0000000000-0x00001fff) dlmb_cntlr dlmb
(0000000000-0x00001fff) ilmb_cntlr ilmb
(0x81000000-0x8100ffff) Ethernet_MAC mb_plb
(0x81400000-0x8140ffff) LEDs_8Bit mb_plb
(0x81800000-0x8180ffff) xps_intc_0 mb_plb
(0x83c00000-0x83c0ffff) xps_timer_1 mb_plb
(0x84000000-0x8400ffff) RS232_DCE mb_plb
(0x84400000-0x8440ffff) debug_module mb_plb
(0x88000000-0x8bffffff) DDR_SDRAM mb_plb
(0x88000000-0x8bffffff) DDR_SDRAM microblaze_0_dxcl
(0x88000000-0x8bffffff) DDR_SDRAM microblaze_0_IXCL
(0x8e000000-0x8effffff) FLASH mb_plb
- Software details
Before reading further; go thru this U-boot porting on Mircroblaze wiki
http://www.monstr.eu/wiki/doku.php - use this for U-boot porting info.
Toolchain - gcc, glibc, binutils. Used pre-built binaries from http://xilinx.wikidot.com/
BSP setup:
BSP setup:
BSP for U-boot is generated importing U-boot device-tree generator in Xilinx EDK. Generating Software Libs for U-boot will create config.mk and xparameters.h files.
Copy the files in U-boot source. Copy config.mk and xparameters.h into board/xilinx/microblaze-generic. It is this board specific xparameters.h that is included by include/configs/microblaze-generic.h file
Compiling:
Compiling:
Please follow the wiki for compiling U-boot.
Running:
Connect Serial terminal (DTE) to the Host machine (I used a USB-RS232 converter cable as my host is a laptop). Open Microsoft hyperterminal (or any other serial terminal), and set Baud to 9600; let all other options be as it is.
U-boot was downloaded using XIlinx XMD debugger. The U-boot elf has to be placed in the root of the project directory. Open XMD, and give the command 'dow u-boot'. For ELF downloaded, PC will be set accordingly to the start of the text section; so we can directly give 'run' command.
Output:
Running:
Connect Serial terminal (DTE) to the Host machine (I used a USB-RS232 converter cable as my host is a laptop). Open Microsoft hyperterminal (or any other serial terminal), and set Baud to 9600; let all other options be as it is.
U-boot was downloaded using XIlinx XMD debugger. The U-boot elf has to be placed in the root of the project directory. Open XMD, and give the command 'dow u-boot'. For ELF downloaded, PC will be set accordingly to the start of the text section; so we can directly give 'run' command.
Output:
Status:
U-boot is up ! Seeing this u-boot prompt is a delight for any bringup/embedded developer imo :)
----------------------------
SDRAM :
Icache:ON
Dcache:OFF
U-Boot Start:0x8bfc0000
Flash: 16 MiB
*** Warning - bad CRC, using default environment
Net: Xilinx_Emaclite
MAC: 00:e0:0c:00:00:fd
U-BOOT for microblaze-generic
U-Boot-S3E>
---------------------------
Issues I faced:
1. Build issue
The following error while compiling U-boot and Linux kernel as well:
kernel/built-in.o: In function `sched_clock_cpu':
/home/sandeep/linux_port/microblaze-fdt/linux-2.6-microblaze/kernel/sched_clock.c:334: relocation truncated to fit: R_MICROBLAZE_32_PCREL_LO against symbol `sched_clock' defined in .text section in arch/microblaze/kernel/built-in.o
I have an older toolchain (seems like this has been resolved in later toolchains); hence the workaround I found was to move the complaining function to a seperate file, and add that new file to the makefile. Compilation will go through fine then.
2. Ping didn't work, though Ethernet device was initialized properly:
Had following 3 issues to be resolved
- Use Cross-over ethernet cable if directly connecting board to the Host.
- Had a MAC address (from board manufacturing) with multicast address bit set. Please see this U-boot wiki on how to create a new MAC address for testing http://www.denx.de/wiki/view/DULG/EthernetDoesNotWork
- Disable firewall in host
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